MemVerge in the News
Endless Memory, Fast Chiplet Interconnects And New M.2 NVMe Client SSDs
MemVerge and SK hynix announced what they call, Project Endless Memory. This is said to be a co-engineered system that addresses the challenge of memory exhaustion in data-intensive applications. Memory exhaustion is a major problem that can cause Out-of-Memory (OOM) crashes or poor performance due to swap usage, especially in clustered environments where memory usage is not uniform across nodes.
MemVerge, SK hynix say memory is endless now
DRAM virtualizer MemVerge has teamed up with SK hynix on what they’re calling Project Endless Memory to run applications needing more memory than is actually attached to the server by using external memory resources accessed by CXL.
MemVerge Demonstrates How CXL Memory Expansion Will Close the Gap
MemVerge® is attending MemCon to demonstrate the capacity and performance benefits of Compute Express Link™ (CXL™) memory. The demo features a server running an online transaction processing (OLTP) benchmark, with Memory Machine™ software from MemVerge that provides tiering for system DIMM and E3.S CXL memory expansion from Micron.
CXL Enabled Memory Innovation with MemVerge
Podcast | TechArena host Allyson Klein chats with Memverge founder and CEO Charles Fan about his company’s disruptive vision for breaking through data center memory limitations and what the CXL standard will bring to infrastructure innovation.
Implementing CXL with MemVerge
At the recent Tech Field Day event, MemVerge brought CXL to the audience. MemVerge is one of the frontline companies paving the way for implementation of CXL. During the event, Sr. Software Architect and Product Manager, Steve Scargall showcased two core CXL products – MemVerge MemoryViewer and Memory Machine, that MemVerge has brought to the market to enable software adoption of CXL.
MemVerge Unveils First Software-Defined CXL Memory Applications to Support 4th Gen AMD EPYC™ Processors
Memory Viewer and Memory Machine software run on 4th generation AMD EPYC processors supporting CXL 1.1+ to deliver memory that can be dynamically pooled, tiered, and shared.